/**
 *****************************************************************************
 * @file     _reg_clkrst.h
 *
 * @brief    -
 *
 * Copyright (C) RealMega 2019-2020
 *
 *****************************************************************************
 */

#ifndef __REG_CLKRST_H__
#define __REG_CLKRST_H__

#include "type_def.h"



//MACROS of register cpu_sys_clk_cfg
#define CLKRST_CPU_SYS_CLK_CFG_REG_CM0P_PCLK_GATE_EN                          (1<<1)
#define CLKRST_CPU_SYS_CLK_CFG_REG_CM0P_APB_REG_CLK_FORCE_ON                  (1<<0)


//MACROS of register apb0_clk_force_cfg
#define CLKRST_APB0_CLK_FORCE_CFG_REG_PMU_INTF_REG_CLK_FORCE_ON               (1<<16)
#define APB0_CLK_FORCE_CFG_REG_CLKRST_REG_CLK_FORCE_ON                        (1<<15)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_SYS_CTRL_REG_CLK_FORCE_ON               (1<<14)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_SPIFLASH_CLK_FORCE_ON                   (1<<13)
#define CLKRST_APB0_CLK_FORCE_CFG_AON_SLEEP_REG_CLK_FORCE_ON                  (1<<12)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_IOMUX_TOP_CLK_FORCE_ON                  (1<<11)
#define APB0_CLK_FORCE_CFG_REG_RFDIG_TOP_REG_CLK_FORCE_ON                     (1<<10)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_CALENDAR_REG_CLK_FORCE_ON               (1<<9)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_QDEC_REG_CLK_FORCE_ON                   (1<<8)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_PWM_REG_CLK_FORCE_ON                    (1<<7)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_PAGE_SPY_REG_CLK_FORCE_ON               (1<<6)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_KEYPAD_REG_CLK_FORCE_ON                 (1<<5)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_TIMER_REG_CLK_FORCE_ON                  (1<<4)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_DBG_HST_REG_CLK_FORCE_ON                (1<<3)
#define APB0_CLK_FORCE_CFG_REG_DBG_HST_PCLK_MODE_UART_FORCE_ON                (1<<2)
#define CLKRST_APB0_CLK_FORCE_CFG_REG_DBG_HST_UART_CLK_FORCE_ON               (1<<1)
#define APB0_CLK_FORCE_CFG_REG_DBG_HST_PCLK_MOD_DBG_FORCE_ON                  (1<<0)


//MACROS of register apb1_clk_force_cfg
#define CLKRST_APB1_CLK_FORCE_CFG_REG_DMA_HCLK_FORCE_ON                       (1<<15)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_DMA_REG_CLK_FORCE_ON                    (1<<14)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SYSIFC_PCLK_FORCE_ON                    (1<<13)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SYSIFC_DBG_HCLK_FORCE_ON                (1<<12)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SYSIFC_CH_HCLK_FORCE_ON_MASK            (0xC00UL)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SYSIFC_CH_HCLK_FORCE_ON(N)              (((N)<<10)&0xC00UL)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SYSIFC_HCLK_FORCE_ON                    (1<<9)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SYS_IFC_REG_CLK_FORCE_ON                (1<<8)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SPI_REG_CLK_FORCE_ON                    (1<<7)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_GPT_REG_CLK_FORCE_ON                    (1<<6)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_IR_REG_CLK_FORCE_ON                     (1<<5)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_UART_REG_CLK_FORCE_ON                   (1<<4)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_MDU_REG_CLK_FORCE_ON                    (1<<3)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_SPI_FUNC_CLK_FORCE                      (1<<2)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_UART0_PCLK_FORCE_ON                     (1<<1)
#define CLKRST_APB1_CLK_FORCE_CFG_REG_UART0_CLK_FORCE_ON                      (1<<0)


//MACROS of register ahb_perl_clk_enable_cfg0
#define CLKRST_AHB_PERL_CLK_ENABLE_CFG0_REG_HCLK_AHB_CACHE_EN                 (1<<3)
#define CLKRST_AHB_PERL_CLK_ENABLE_CFG0_REG_SPIFLASH_CLK_EN                   (1<<2)
#define CLKRST_AHB_PERL_CLK_ENABLE_CFG0_REG_HCLK_SPIFLASH_EN                  (1<<1)
#define CLKRST_AHB_PERL_CLK_ENABLE_CFG0_REG_HCLK_AHB_PER_EN                   (1<<0)


//MACROS of register apb0_clk_enable_cfg
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_CLK_ENABLE_KEYPAD                      (1<<19)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_AON_SLEEP_PCLK_EN                      (1<<18)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_SYS_CTRL_PCLK_EN                       (1<<17)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_IOMUX_TOP_PCLK_EN                      (1<<16)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_PMUIF_PCLK_EN                          (1<<15)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_SYSWDT_CLK_EN                          (1<<14)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_KEYPAD_PCLK_EN                         (1<<13)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_PCLK_PAGE_SPY_EN                       (1<<12)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_HCLK_PAGE_SPY_EN                       (1<<11)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_PWM_PCLK_EN                            (1<<10)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_PWM_OSC_CLK_EN                         (1<<9)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_QDEC_PCLK_EN                           (1<<8)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_CALENDAR_PCLK_EN                       (1<<7)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_RFDIG_TOP_PCLK_EN                      (1<<6)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_DBG_HST_PCLK_ALWAYS_EN                 (1<<5)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_APB0_HCLK_EN                           (1<<4)
#define CLKRST_APB0_CLK_ENABLE_CFG_REG_DBG_HST_PCLK_EN                        (1<<3)


//MACROS of register apb1_clk_enable_cfg
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_DW_I2C_PCLK_EN                         (1<<12)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_DW_I2C_IC_CLK_EN                       (1<<11)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_BT_CORE_PCLK_EN                        (1<<10)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_IR_PCLK_EN                             (1<<9)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_SPI_PCLK_EN                            (1<<8)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_GPT_PCLK_EN                            (1<<7)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_GPT_CLK_T0_EN                          (1<<6)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_GPT_CLK_S_EN                           (1<<5)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_MDU_CLK_EN                             (1<<4)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_MDU_PCLK_EN                            (1<<3)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_DMA_PCLK_EN                            (1<<2)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_IR_SYS_CLK_EN                          (1<<1)
#define CLKRST_APB1_CLK_ENABLE_CFG_REG_IR_CLK_EN                              (1<<0)


//MACROS of register mem_clk_cfg
#define CLKRST_MEM_CLK_CFG_REG_BT_RAM_AUTO_CKG                                (1<<9)
#define CLKRST_MEM_CLK_CFG_REG_ROM_AUTO_CKG                                   (1<<8)
#define CLKRST_MEM_CLK_CFG_REG_RAM0_AUTO_CKG                                  (1<<7)
#define CLKRST_MEM_CLK_CFG_REG_RAM1_AUTO_CKG                                  (1<<6)
#define CLKRST_MEM_CLK_CFG_REG_ROM0_AUTO_CKG                                  (1<<5)
#define CLKRST_MEM_CLK_CFG_REG_ROM1_AUTO_CKG                                  (1<<4)
#define CLKRST_MEM_CLK_CFG_REG_ROM2_AUTO_CKG                                  (1<<3)
#define CLKRST_MEM_CLK_CFG_REG_RAM1_0_AUTO_CKG                                (1<<2)
#define CLKRST_MEM_CLK_CFG_REG_RAM1_1_AUTO_CKG                                (1<<1)
#define CLKRST_MEM_CLK_CFG_REG_RAM1_2_AUTO_CKG                                (1<<0)


//MACROS of register hf0_hf1_cfg
#define CLKRST_HF0_HF1_CFG_REG_HF0_CLK_EN                                     (1<<13)
#define CLKRST_HF0_HF1_CFG_REG_HF0_CLK_DIV_MASK                               (0x1F00UL)
#define CLKRST_HF0_HF1_CFG_REG_HF0_CLK_DIV(N)                                 (((N)<<8)&0x1F00UL)
#define CLKRST_HF0_HF1_CFG_REG_HF0_CLK_CFG_SET                                (1<<7)
#define CLKRST_HF0_HF1_CFG_REG_HF1_CLK_EN                                     (1<<6)
#define CLKRST_HF0_HF1_CFG_REG_HF1_CLK_DIV_MASK                               (0x3EUL)
#define CLKRST_HF0_HF1_CFG_REG_HF1_CLK_DIV(N)                                 (((N)<<1)&0x3EUL)
#define CLKRST_HF0_HF1_CFG_REG_HF1_CLK_CFG_SET                                (1<<0)


//MACROS of register root_clk_cfg
#define CLKRST_ROOT_CLK_CFG_REG_CLK_4M_DIV_DR                                 (1<<20)
#define CLKRST_ROOT_CLK_CFG_REG_CLK_4M_DIV_MASK                               (0xF0000UL)
#define CLKRST_ROOT_CLK_CFG_REG_CLK_4M_DIV(N)                                 (((N)<<16)&0xF0000UL)
#define CLKRST_ROOT_CLK_CFG_REG_CLK_4M_CFG_SET                                (1<<15)
#define CLKRST_ROOT_CLK_CFG_REG_CLK_4M_EN                                     (1<<14)
#define CLKRST_ROOT_CLK_CFG_REG_APB0_ROOT_PCLK_EN                             (1<<13)
#define CLKRST_ROOT_CLK_CFG_REG_APB0_ROOT_PCLK_DIV_MASK                       (0x1F00UL)
#define CLKRST_ROOT_CLK_CFG_REG_APB0_ROOT_PCLK_DIV(N)                         (((N)<<8)&0x1F00UL)
#define CLKRST_ROOT_CLK_CFG_REG_APB0_ROOT_PCLK_CFG_SET                        (1<<7)
#define CLKRST_ROOT_CLK_CFG_REG_APB1_ROOT_PCLK_EN                             (1<<6)
#define CLKRST_ROOT_CLK_CFG_REG_APB1_ROOT_PCLK_DIV_MASK                       (0x3EUL)
#define CLKRST_ROOT_CLK_CFG_REG_APB1_ROOT_PCLK_DIV(N)                         (((N)<<1)&0x3EUL)
#define CLKRST_ROOT_CLK_CFG_REG_APB1_ROOT_PCLK_CFG_SET                        (1<<0)


//MACROS of register cpu_root_cfg
#define CLKRST_CPU_ROOT_CFG_REG_CPU_ROOT_CLK_SEL_EN                           (1<<23)
#define CLKRST_CPU_ROOT_CFG_REG_CPU_ROOT_CLK_SEL_MASK                         (0x600000UL)
#define CLKRST_CPU_ROOT_CFG_REG_CPU_ROOT_CLK_SEL(N)                           (((N)<<21)&0x600000UL)
#define CLKRST_CPU_ROOT_CFG_REG_CLK2DIG_DIV_CPU_ROOT_EN                       (1<<20)
#define CLKRST_CPU_ROOT_CFG_REG_CLK2DIG_DIV_CPU_ROOT_DIV_MASK                 (0xF8000UL)
#define CLKRST_CPU_ROOT_CFG_REG_CLK2DIG_DIV_CPU_ROOT_DIV(N)                   (((N)<<15)&0xF8000UL)
#define REG_CLK2DIG_DIV_CPU_ROOT_CFG_SET                                      (1<<14)
#define CPU_ROOT_CFG_REG_CLK2DIG_DOUBLE_DIV_CPU_ROOT_EN                       (1<<13)
#define CPU_ROOT_CFG_REG_CLK2DIG_DOUBLE_DIV_CPU_ROOT_DIV_MASK                 (0x1F00UL)
#define CPU_ROOT_CFG_REG_CLK2DIG_DOUBLE_DIV_CPU_ROOT_DIV(N)                   (((N)<<8)&0x1F00UL)
#define REG_CLK2DIG_DOUBLE_DIV_CPU_ROOT_CFG_SET                               (1<<7)
#define CPU_ROOT_CFG_REG_CLK_LPO54M_DIV_CPU_ROOT_EN                           (1<<6)
#define CPU_ROOT_CFG_REG_CLK_LPO54M_DIV_CPU_ROOT_DIV_MASK                     (0x3EUL)
#define CPU_ROOT_CFG_REG_CLK_LPO54M_DIV_CPU_ROOT_DIV(N)                       (((N)<<1)&0x3EUL)
#define REG_CLK_LPO54M_DIV_CPU_ROOT_CFG_SET                                   (1<<0)


//MACROS of register spiflash_root_cfg
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_SEL_EN                 (1<<9)
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_SEL_MASK               (0x180UL)
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_SEL(N)                 (((N)<<7)&0x180UL)
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_EN                     (1<<6)
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_DIV_MASK               (0x3EUL)
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_DIV(N)                 (((N)<<1)&0x3EUL)
#define CLKRST_SPIFLASH_ROOT_CFG_REG_SPIFLASH_ROOT_CLK_CFG_SET                (1<<0)


//MACROS of register i2c_root_clk_cfg
#define CLKRST_I2C_ROOT_CLK_CFG_REG_I2C_ROOT_CLK_SEL_EN                       (1<<9)
#define CLKRST_I2C_ROOT_CLK_CFG_REG_I2C_ROOT_CLK_SEL_MASK                     (0x180UL)
#define CLKRST_I2C_ROOT_CLK_CFG_REG_I2C_ROOT_CLK_SEL(N)                       (((N)<<7)&0x180UL)
#define CLKRST_I2C_ROOT_CLK_CFG_REG_I2C_ROOT_CLK_EN                           (1<<6)
#define CLKRST_I2C_ROOT_CLK_CFG_REG_I2C_ROOT_CLK_DIV_MASK                     (0x3EUL)
#define CLKRST_I2C_ROOT_CLK_CFG_REG_I2C_ROOT_CLK_DIV(N)                       (((N)<<1)&0x3EUL)
#define CLKRST_REG_I2C_ROOT_CLK_CFG_SET                                       (1<<0)


//MACROS of register ir_sys_root_clk_cfg
#define CLKRST_IR_SYS_ROOT_CLK_CFG_REG_IR_CLK_SEL                             (1<<7)
#define CLKRST_IR_SYS_ROOT_CLK_CFG_REG_IR_SYS_ROOT_CLK_EN                     (1<<6)
#define CLKRST_IR_SYS_ROOT_CLK_CFG_REG_IR_SYS_ROOT_CLK_DIV_MASK               (0x3EUL)
#define CLKRST_IR_SYS_ROOT_CLK_CFG_REG_IR_SYS_ROOT_CLK_DIV(N)                 (((N)<<1)&0x3EUL)
#define CLKRST_REG_IR_SYS_ROOT_CLK_CFG_SET                                    (1<<0)


//MACROS of register uart0_root_cfg
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_SEL_EN                       (1<<26)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_SEL_MASK                     (0x3000000UL)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_SEL(N)                       (((N)<<24)&0x3000000UL)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_EN                           (1<<23)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_NUM_MASK                     (0x7FF000UL)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_NUM(N)                       (((N)<<12)&0x7FF000UL)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_DENOM_MASK                   (0xFFEUL)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_DENOM(N)                     (((N)<<1)&0xFFEUL)
#define CLKRST_UART0_ROOT_CFG_REG_UART0_ROOT_CLK_CFG_SET                      (1<<0)


//MACROS of register lf_clk_cfg
#define CLKRST_LF_CLK_CFG_REG_LF_CLK_SEL_EN                                   (1<<2)
#define CLKRST_LF_CLK_CFG_REG_LF_CLK_SEL_MASK                                 (0x3UL)
#define CLKRST_LF_CLK_CFG_REG_LF_CLK_SEL(N)                                   (((N)<<0)&0x3UL)


//MACROS of register bt_clk_cfg
#define CLKRST_BT_CLK_CFG_REG_BT_MASTER_CLK_DIV_MASK                          (0xE0UL)
#define CLKRST_BT_CLK_CFG_REG_BT_MASTER_CLK_DIV(N)                            (((N)<<5)&0xE0UL)
#define CLKRST_BT_CLK_CFG_REG_BT_MASTER_CLK_CFG_SET                           (1<<4)
#define CLKRST_BT_CLK_CFG_REG_BT_MASTER_CLK_DIV_EN                            (1<<3)
#define CLKRST_BT_CLK_CFG_REG_BT_REF_CLK_EN                                   (1<<2)
#define CLKRST_BT_CLK_CFG_REG_DBM_HCLK_EN                                     (1<<1)
#define CLKRST_BT_CLK_CFG_REG_BT_HCLK_EN                                      (1<<0)


//MACROS of register resetn_src0
#define CLKRST_RESETN_SRC0_REG_CM0P_GPIO_HRESETN                              (1<<29)
#define CLKRST_RESETN_SRC0_REG_HRESETN_AHB_PER                                (1<<28)
#define CLKRST_RESETN_SRC0_REG_HRESETN_SPIFLASH                               (1<<27)
#define CLKRST_RESETN_SRC0_REG_HRESETN_AHB_CACHE                              (1<<26)
#define CLKRST_RESETN_SRC0_REG_APB0_HRESETN                                   (1<<25)
#define CLKRST_RESETN_SRC0_REG_DBG_HST_PRESETN                                (1<<24)
#define CLKRST_RESETN_SRC0_REG_DBG_HST_UART_RSTB                              (1<<23)
#define CLKRST_RESETN_SRC0_REG_DBG_HST_REG_RSTB                               (1<<22)
#define CLKRST_RESETN_SRC0_REG_DBG_HST_HW_RSTB                                (1<<21)
#define CLKRST_RESETN_SRC0_REG_IOMUX_TOP_PRESETN                              (1<<20)
#define RESETN_SRC0_REG_CLKRST_CFG_PRESETN                                    (1<<19)
#define CLKRST_RESETN_SRC0_REG_PRESETN_AON                                    (1<<18)
#define CLKRST_RESETN_SRC0_REG_CM0P_PRESETN                                   (1<<17)
#define CLKRST_RESETN_SRC0_REG_TIMER_PRESETN                                  (1<<16)
#define CLKRST_RESETN_SRC0_REG_SYSWDT_RSTB                                    (1<<15)
#define CLKRST_RESETN_SRC0_REG_KEYPAD_PRESETN                                 (1<<14)
#define CLKRST_RESETN_SRC0_REG_PRESETN_PAGE_SPY                               (1<<13)
#define CLKRST_RESETN_SRC0_REG_HRESETN_PAGE_SPY                               (1<<12)
#define CLKRST_RESETN_SRC0_REG_PWM_PRESETN                                    (1<<11)
#define CLKRST_RESETN_SRC0_REG_PWM_RESETN                                     (1<<10)
#define CLKRST_RESETN_SRC0_REG_QDEC_PRESETN                                   (1<<9)
#define CLKRST_RESETN_SRC0_REG_CALENDAR_PRESETN                               (1<<8)
#define CLKRST_RESETN_SRC0_REG_AON_SLEEP_PRESETN                              (1<<7)
#define CLKRST_RESETN_SRC0_REG_DW_I2C_PRESETN                                 (1<<6)
#define CLKRST_RESETN_SRC0_REG_DW_I2C_IC_RST_N                                (1<<5)
#define CLKRST_RESETN_SRC0_REG_APB1_PRESETN                                   (1<<4)
#define CLKRST_RESETN_SRC0_REG_UART0_RSTB                                     (1<<3)
#define CLKRST_RESETN_SRC0_REG_IR_RSTB                                        (1<<2)
#define CLKRST_RESETN_SRC0_REG_IR_SYS_RESETN                                  (1<<1)
#define CLKRST_RESETN_SRC0_REG_SPI_PRESETN                                    (1<<0)


//MACROS of register resetn_src1
#define CLKRST_RESETN_SRC1_REG_GPT_RSTB                                       (1<<31)
#define CLKRST_RESETN_SRC1_REG_MDU_RSTB                                       (1<<30)
#define CLKRST_RESETN_SRC1_REG_MDU_PRESETN                                    (1<<29)
#define CLKRST_RESETN_SRC1_REG_SYSIFC_HRESETN                                 (1<<28)
#define CLKRST_RESETN_SRC1_REG_SYSIFC_PRESETN                                 (1<<27)
#define CLKRST_RESETN_SRC1_REG_DMA_HRESETN                                    (1<<26)
#define CLKRST_RESETN_SRC1_REG_SSP0_RESETN                                    (1<<25)
#define CLKRST_RESETN_SRC1_REG_DMA_PRESETN                                    (1<<24)
#define CLKRST_RESETN_SRC1_REG_BT_CORE_PRESETN                                (1<<23)
#define CLKRST_RESETN_SRC1_REG_SYS_CTRL_PRESETN                               (1<<22)
#define CLKRST_RESETN_SRC1_REG_IR_PRESETN                                     (1<<21)
#define CLKRST_RESETN_SRC1_REG_PMUIF_PRESETN                                  (1<<20)
#define CLKRST_RESETN_SRC1_REG_SPIFLASH_RSTN                                  (1<<19)
#define CLKRST_RESETN_SRC1_REG_CPU_SLEEP_RSTB                                 (1<<18)
#define CLKRST_RESETN_SRC1_REG_GPT_PRESETN                                    (1<<17)
#define CLKRST_RESETN_SRC1_REG_UART0_PRESETN                                  (1<<16)
#define CLKRST_RESETN_SRC1_REG_RESETN_RF                                      (1<<15)
#define CLKRST_RESETN_SRC1_REG_BT_REF_RSTN                                    (1<<14)
#define CLKRST_RESETN_SRC1_REG_BT_HRESETN                                     (1<<13)
#define CLKRST_RESETN_SRC1_REG_BT_MASTER_RSTN                                 (1<<12)


//MACROS of register cpu_stclk_cfg
#define CLKRST_CPU_STCLK_CFG_REG_CPU_STCLK_CLK_SEL_EN                         (1<<2)
#define CLKRST_CPU_STCLK_CFG_REG_CPU_STCLK_CLK_SEL_MASK                       (0x3UL)
#define CLKRST_CPU_STCLK_CFG_REG_CPU_STCLK_CLK_SEL(N)                         (((N)<<0)&0x3UL)


//MACROS of register timer_clk_cfg
#define CLKRST_TIMER_CLK_CFG_REG_KEYPAD_CLK32K_SEL_EN                         (1<<10)
#define CLKRST_TIMER_CLK_CFG_REG_KEYPAD_CLK32K_SEL_MASK                       (0x300UL)
#define CLKRST_TIMER_CLK_CFG_REG_KEYPAD_CLK32K_SEL(N)                         (((N)<<8)&0x300UL)
#define CLKRST_TIMER_CLK_CFG_REG_SYSWDT_CLK32K_SEL_EN                         (1<<7)
#define CLKRST_TIMER_CLK_CFG_REG_SYSWDT_CLK32K_SEL_MASK                       (0x60UL)
#define CLKRST_TIMER_CLK_CFG_REG_SYSWDT_CLK32K_SEL(N)                         (((N)<<5)&0x60UL)
#define CLKRST_TIMER_CLK_CFG_REG_HWTIMER_CLK32K_SEL_EN                        (1<<4)
#define CLKRST_TIMER_CLK_CFG_REG_HWTIMER_CLK32K_SEL_MASK                      (0xCUL)
#define CLKRST_TIMER_CLK_CFG_REG_HWTIMER_CLK32K_SEL(N)                        (((N)<<2)&0xCUL)
#define CLKRST_TIMER_CLK_CFG_REG_TIMER_PCLK_EN                                (1<<1)
#define CLKRST_TIMER_CLK_CFG_REG_HWTIMER_CLK_EN                               (1<<0)


//MACROS of register gpt_clk_cfg
#define CLKRST_GPT_CLK_CFG_REG_GPT_CLK_T0_SEL_EN                              (1<<2)
#define CLKRST_GPT_CLK_CFG_REG_GPT_CLK_T0_SEL_MASK                            (0x3UL)
#define CLKRST_GPT_CLK_CFG_REG_GPT_CLK_T0_SEL(N)                              (((N)<<0)&0x3UL)


//MACROS of register dbg_hst_clk_cfg
#define DBG_HST_CLK_CFG_REG_DBG_HST_UART_CLK_LD_CFG_SET                       (1<<23)
#define CLKRST_DBG_HST_CLK_CFG_REG_DBG_HST_EN                                 (1<<22)
#define CLKRST_DBG_HST_CLK_CFG_REG_DBG_HST_UART_CLK_NUM_MASK                  (0x3FF800UL)
#define CLKRST_DBG_HST_CLK_CFG_REG_DBG_HST_UART_CLK_NUM(N)                    (((N)<<11)&0x3FF800UL)
#define CLKRST_DBG_HST_CLK_CFG_REG_DBG_HST_UART_CLK_DENOM_MASK                (0x7FFUL)
#define CLKRST_DBG_HST_CLK_CFG_REG_DBG_HST_UART_CLK_DENOM(N)                  (((N)<<0)&0x7FFUL)


//MACROS of register cpu_root_32k_cfg
#define CLKRST_CPU_ROOT_32K_CFG_REG_CPU_ROOT_CLK_32K_SEL_EN                   (1<<2)
#define CLKRST_CPU_ROOT_32K_CFG_REG_CPU_ROOT_CLK_32K_SEL_MASK                 (0x3UL)
#define CLKRST_CPU_ROOT_32K_CFG_REG_CPU_ROOT_CLK_32K_SEL(N)                   (((N)<<0)&0x3UL)



//cpu_sys_clk_cfg, offset:0x0
typedef union
{
    u32 v;
    struct
    {
        u32  reg_cm0p_apb_reg_clk_force_on           :1; /*[0], RW, 1'h1, */
        u32  reg_cm0p_pclk_gate_en                   :1; /*[1], RW, 1'h1, */
        u32  reserved0                               :30; /*[31:2], RO, 30'h0, */
    }b;
}t_clkrst_cpu_sys_clk_cfg;


//apb0_clk_force_cfg, offset:0x4
typedef union
{
    u32 v;
    struct
    {
        u32  reg_dbg_hst_pclk_mod_dbg_force_on       :1; /*[0], RW, 1'h1, */
        u32  reg_dbg_hst_uart_clk_force_on           :1; /*[1], RW, 1'h1, */
        u32  reg_dbg_hst_pclk_mode_uart_force_on     :1; /*[2], RW, 1'h1, */
        u32  reg_dbg_hst_reg_clk_force_on            :1; /*[3], RW, 1'h1, */
        u32  reg_timer_reg_clk_force_on              :1; /*[4], RW, 1'h1, */
        u32  reg_keypad_reg_clk_force_on             :1; /*[5], RW, 1'h1, */
        u32  reg_page_spy_reg_clk_force_on           :1; /*[6], RW, 1'h1, */
        u32  reg_pwm_reg_clk_force_on                :1; /*[7], RW, 1'h1, */
        u32  reg_qdec_reg_clk_force_on               :1; /*[8], RW, 1'h1, */
        u32  reg_calendar_reg_clk_force_on           :1; /*[9], RW, 1'h1, */
        u32  reg_rfdig_top_reg_clk_force_on          :1; /*[10], RW, 1'h1, */
        u32  reg_iomux_top_clk_force_on              :1; /*[11], RW, 1'h1, */
        u32  aon_sleep_reg_clk_force_on              :1; /*[12], RW, 1'h1, */
        u32  reg_spiflash_clk_force_on               :1; /*[13], RW, 1'h1, */
        u32  reg_sys_ctrl_reg_clk_force_on           :1; /*[14], RW, 1'h1, */
        u32  reg_clkrst_reg_clk_force_on             :1; /*[15], RW, 1'h1, */
        u32  reg_pmu_intf_reg_clk_force_on           :1; /*[16], RW, 1'h1, */
        u32  reserved0                               :15; /*[31:17], RO, 15'h0, */
    }b;
}t_clkrst_apb0_clk_force_cfg;


//apb1_clk_force_cfg, offset:0x8
typedef union
{
    u32 v;
    struct
    {
        u32  reg_uart0_clk_force_on                  :1; /*[0], RW, 1'h1, */
        u32  reg_uart0_pclk_force_on                 :1; /*[1], RW, 1'h1, */
        u32  reg_spi_func_clk_force                  :1; /*[2], RW, 1'h1, */
        u32  reg_mdu_reg_clk_force_on                :1; /*[3], RW, 1'h1, */
        u32  reg_uart_reg_clk_force_on               :1; /*[4], RW, 1'h1, */
        u32  reg_ir_reg_clk_force_on                 :1; /*[5], RW, 1'h1, */
        u32  reg_gpt_reg_clk_force_on                :1; /*[6], RW, 1'h1, */
        u32  reg_spi_reg_clk_force_on                :1; /*[7], RW, 1'h1, */
        u32  reg_sys_ifc_reg_clk_force_on            :1; /*[8], RW, 1'h1, */
        u32  reg_sysifc_hclk_force_on                :1; /*[9], RW, 1'h1, */
        u32  reg_sysifc_ch_hclk_force_on             :2; /*[11:10], RW, 2'h3, */
        u32  reg_sysifc_dbg_hclk_force_on            :1; /*[12], RW, 1'h1, */
        u32  reg_sysifc_pclk_force_on                :1; /*[13], RW, 1'h1, */
        u32  reg_dma_reg_clk_force_on                :1; /*[14], RW, 1'h1, */
        u32  reg_dma_hclk_force_on                   :1; /*[15], RW, 1'h1, */
        u32  reserved0                               :16; /*[31:16], RO, 16'h0, */
    }b;
}t_clkrst_apb1_clk_force_cfg;


//ahb_perl_clk_enable_cfg0, offset:0xc
typedef union
{
    u32 v;
    struct
    {
        u32  reg_hclk_ahb_per_en                     :1; /*[0], RW, 1'h1, */
        u32  reg_hclk_spiflash_en                    :1; /*[1], RW, 1'h1, */
        u32  reg_spiflash_clk_en                     :1; /*[2], RW, 1'h1, */
        u32  reg_hclk_ahb_cache_en                   :1; /*[3], RW, 1'h1, */
        u32  reserved0                               :28; /*[31:4], RO, 28'h0, */
    }b;
}t_clkrst_ahb_perl_clk_enable_cfg0;


//apb0_clk_enable_cfg, offset:0x10
typedef union
{
    u32 v;
    struct
    {
        u32  reserved1                               :3; /*[2:0], RO, 3'h0, */
        u32  reg_dbg_hst_pclk_en                     :1; /*[3], RW, 1'h1, */
        u32  reg_apb0_hclk_en                        :1; /*[4], RW, 1'h1, */
        u32  reg_dbg_hst_pclk_always_en              :1; /*[5], RW, 1'h1, */
        u32  reg_rfdig_top_pclk_en                   :1; /*[6], RW, 1'h1, */
        u32  reg_calendar_pclk_en                    :1; /*[7], RW, 1'h1, */
        u32  reg_qdec_pclk_en                        :1; /*[8], RW, 1'h1, */
        u32  reg_pwm_osc_clk_en                      :1; /*[9], RW, 1'h1, */
        u32  reg_pwm_pclk_en                         :1; /*[10], RW, 1'h1, */
        u32  reg_hclk_page_spy_en                    :1; /*[11], RW, 1'h1, */
        u32  reg_pclk_page_spy_en                    :1; /*[12], RW, 1'h1, */
        u32  reg_keypad_pclk_en                      :1; /*[13], RW, 1'h1, */
        u32  reg_syswdt_clk_en                       :1; /*[14], RW, 1'h1, */
        u32  reg_pmuif_pclk_en                       :1; /*[15], RW, 1'h1, */
        u32  reg_iomux_top_pclk_en                   :1; /*[16], RW, 1'h1, */
        u32  reg_sys_ctrl_pclk_en                    :1; /*[17], RW, 1'h1, */
        u32  reg_aon_sleep_pclk_en                   :1; /*[18], RW, 1'h1, */
        u32  reg_clk_enable_keypad                   :1; /*[19], RW, 1'h1, */
        u32  reserved0                               :12; /*[31:20], RO, 12'h0, */
    }b;
}t_clkrst_apb0_clk_enable_cfg;


//apb1_clk_enable_cfg, offset:0x14
typedef union
{
    u32 v;
    struct
    {
        u32  reg_ir_clk_en                           :1; /*[0], RW, 1'h1, */
        u32  reg_ir_sys_clk_en                       :1; /*[1], RW, 1'h1, */
        u32  reg_dma_pclk_en                         :1; /*[2], RW, 1'h1, */
        u32  reg_mdu_pclk_en                         :1; /*[3], RW, 1'h1, */
        u32  reg_mdu_clk_en                          :1; /*[4], RW, 1'h1, */
        u32  reg_gpt_clk_s_en                        :1; /*[5], RW, 1'h1, */
        u32  reg_gpt_clk_t0_en                       :1; /*[6], RW, 1'h1, */
        u32  reg_gpt_pclk_en                         :1; /*[7], RW, 1'h1, */
        u32  reg_spi_pclk_en                         :1; /*[8], RW, 1'h1, */
        u32  reg_ir_pclk_en                          :1; /*[9], RW, 1'h1, */
        u32  reg_bt_core_pclk_en                     :1; /*[10], RW, 1'h1, */
        u32  reg_dw_i2c_ic_clk_en                    :1; /*[11], RW, 1'h1, */
        u32  reg_dw_i2c_pclk_en                      :1; /*[12], RW, 1'h1, */
        u32  reserved0                               :19; /*[31:13], RO, 19'h0, */
    }b;
}t_clkrst_apb1_clk_enable_cfg;


//mem_clk_cfg, offset:0x18
typedef union
{
    u32 v;
    struct
    {
        u32  reg_ram1_2_auto_ckg                     :1; /*[0], RW, 1'h0, */
        u32  reg_ram1_1_auto_ckg                     :1; /*[1], RW, 1'h0, */
        u32  reg_ram1_0_auto_ckg                     :1; /*[2], RW, 1'h0, */
        u32  reg_rom2_auto_ckg                       :1; /*[3], RW, 1'h0, */
        u32  reg_rom1_auto_ckg                       :1; /*[4], RW, 1'h0, */
        u32  reg_rom0_auto_ckg                       :1; /*[5], RW, 1'h0, */
        u32  reg_ram1_auto_ckg                       :1; /*[6], RW, 1'h0, */
        u32  reg_ram0_auto_ckg                       :1; /*[7], RW, 1'h0, */
        u32  reg_rom_auto_ckg                        :1; /*[8], RW, 1'h0, */
        u32  reg_bt_ram_auto_ckg                     :1; /*[9], RW, 1'h0, */
        u32  reserved0                               :22; /*[31:10], RO, 22'h0, */
    }b;
}t_clkrst_mem_clk_cfg;


//hf0_hf1_cfg, offset:0x1c
typedef union
{
    u32 v;
    struct
    {
        u32  reg_hf1_clk_cfg_set                     :1; /*[0], W1S, 1'h0, To enable new reg_hf1_clk_div, reg_hf1_clk_cfg_set needs to be set when or after updating reg_hf1_clk_div.*/
        u32  reg_hf1_clk_div                         :5; /*[5:1], RW, 5'h0, */
        u32  reg_hf1_clk_en                          :1; /*[6], RW, 1'h1, */
        u32  reg_hf0_clk_cfg_set                     :1; /*[7], W1S, 1'h0, To enable new reg_hf0_clk_div, reg_hf0_clk_cfg_set needs to be set when or after updating reg_hf0_clk_div.*/
        u32  reg_hf0_clk_div                         :5; /*[12:8], RW, 5'h0, */
        u32  reg_hf0_clk_en                          :1; /*[13], RW, 1'h1, */
        u32  reserved0                               :18; /*[31:14], RO, 18'h0, */
    }b;
}t_clkrst_hf0_hf1_cfg;


//root_clk_cfg, offset:0x20
typedef union
{
    u32 v;
    struct
    {
        u32  reg_apb1_root_pclk_cfg_set              :1; /*[0], W1S, 1'h0, To enable new reg_apb1_root_pclk_div, reg_apb1_root_pclk_cfg_set needs to be set when or after updating reg_apb1_root_pclk_div.*/
        u32  reg_apb1_root_pclk_div                  :5; /*[5:1], RW, 5'h0, */
        u32  reg_apb1_root_pclk_en                   :1; /*[6], RW, 1'h1, */
        u32  reg_apb0_root_pclk_cfg_set              :1; /*[7], W1S, 1'h0, To enable new reg_apb0_root_pclk_div, reg_apb0_root_pclk_cfg_set needs to be set when or after updating reg_apb0_root_pclk_div.*/
        u32  reg_apb0_root_pclk_div                  :5; /*[12:8], RW, 5'h0, */
        u32  reg_apb0_root_pclk_en                   :1; /*[13], RW, 1'h1, */
        u32  reg_clk_4m_en                           :1; /*[14], RW, 1'h1, */
        u32  reg_clk_4m_cfg_set                      :1; /*[15], W1S, 1'h0, To enable new reg_clk_4m_div, reg_clk_4m_cfg_set needs to be set when or after updating reg_clk_4m_div.*/
        u32  reg_clk_4m_div                          :4; /*[19:16], RW, 4'h8, */
        u32  reg_clk_4m_div_dr                       :1; /*[20], RW, 1'h0, 0, derive clk_4m_div per xtal_type; 1, clk_4m_div from reg_clk_4m_div.*/
        u32  reserved0                               :11; /*[31:21], RO, 11'h0, */
    }b;
}t_clkrst_root_clk_cfg;


//cpu_root_cfg, offset:0x24
typedef union
{
    u32 v;
    struct
    {
        u32  reg_clk_lpo54m_div_cpu_root_cfg_set     :1; /*[0], W1S, 1'h0, To enable new reg_clk_lpo54m_div_cpu_root_div, reg_clk_lpo54m_div_cpu_root_cfg_set needs to be set when or after updating reg_clk_lpo54m_div_cpu_root_div.*/
        u32  reg_clk_lpo54m_div_cpu_root_div         :5; /*[5:1], RW, 5'h0, */
        u32  reg_clk_lpo54m_div_cpu_root_en          :1; /*[6], RW, 1'h0, */
        u32  reg_clk2dig_double_div_cpu_root_cfg_set :1; /*[7], W1S, 1'h0, To enable new reg_clk2dig_double_div_cpu_root_div, reg_clk2dig_double_div_cpu_root_cfg_set needs to be set when or after updating reg_clk2dig_double_div_cpu_root_div.*/
        u32  reg_clk2dig_double_div_cpu_root_div     :5; /*[12:8], RW, 5'h0, */
        u32  reg_clk2dig_double_div_cpu_root_en      :1; /*[13], RW, 1'h0, */
        u32  reg_clk2dig_div_cpu_root_cfg_set        :1; /*[14], W1S, 1'h0, To enable new reg_clk2dig_div_cpu_root_div, reg_clk2dig_div_cpu_root_cfg_set needs to be set when or after updating reg_clk2dig_div_cpu_root_div.*/
        u32  reg_clk2dig_div_cpu_root_div            :5; /*[19:15], RW, 5'h1, */
        u32  reg_clk2dig_div_cpu_root_en             :1; /*[20], RW, 1'h1, */
        u32  reg_cpu_root_clk_sel                    :2; /*[22:21], RW, 2'h0, */
        u32  reg_cpu_root_clk_sel_en                 :1; /*[23], RW, 1'h1, */
        u32  reserved0                               :8; /*[31:24], RO, 8'h0, */
    }b;
}t_clkrst_cpu_root_cfg;


//spiflash_root_cfg, offset:0x28
typedef union
{
    u32 v;
    struct
    {
        u32  reg_spiflash_root_clk_cfg_set           :1; /*[0], W1S, 1'h0, To enable new reg_spiflash_root_clk_div, reg_spiflash_root_clk_cfg_set needs to be set when or after updating reg_spiflash_root_clk_div.*/
        u32  reg_spiflash_root_clk_div               :5; /*[5:1], RW, 5'h0, */
        u32  reg_spiflash_root_clk_en                :1; /*[6], RW, 1'h1, */
        u32  reg_spiflash_root_clk_sel               :2; /*[8:7], RW, 2'h0, */
        u32  reg_spiflash_root_clk_sel_en            :1; /*[9], RW, 1'h1, */
        u32  reserved0                               :22; /*[31:10], RO, 22'h0, */
    }b;
}t_clkrst_spiflash_root_cfg;


//i2c_root_clk_cfg, offset:0x2c
typedef union
{
    u32 v;
    struct
    {
        u32  reg_i2c_root_clk_cfg_set                :1; /*[0], W1S, 1'h0, To enable new reg_i2c_root_clk_div, reg_i2c_root_clk_cfg_set needs to be set when or after updating reg_i2c_root_clk_div.*/
        u32  reg_i2c_root_clk_div                    :5; /*[5:1], RW, 5'h0, */
        u32  reg_i2c_root_clk_en                     :1; /*[6], RW, 1'h1, */
        u32  reg_i2c_root_clk_sel                    :2; /*[8:7], RW, 2'h0, */
        u32  reg_i2c_root_clk_sel_en                 :1; /*[9], RW, 1'h1, */
        u32  reserved0                               :22; /*[31:10], RO, 22'h0, */
    }b;
}t_clkrst_i2c_root_clk_cfg;


//ir_sys_root_clk_cfg, offset:0x30
typedef union
{
    u32 v;
    struct
    {
        u32  reg_ir_sys_root_clk_cfg_set             :1; /*[0], W1S, 1'h0, To enable new reg_ir_sys_root_clk_div, reg_ir_sys_root_clk_cfg_set needs to be set when or after updating reg_ir_sys_root_clk_div.*/
        u32  reg_ir_sys_root_clk_div                 :5; /*[5:1], RW, 5'h0, */
        u32  reg_ir_sys_root_clk_en                  :1; /*[6], RW, 1'h1, */
        u32  reg_ir_clk_sel                          :1; /*[7], RW, 1'h0, 0: select 32k rtc clock as ir operation clock; 1: select 4Mhz clk_4m clock as ir operation clock. Note: ir operation clock is not ir_sys_clk! Best ir clock switching practice: clear reg_ir_clk_en first, then change reg_ir_clk_sel, and finally restore reg_ir_clk_en to 1.*/
        u32  reserved0                               :24; /*[31:8], RO, 24'h0, */
    }b;
}t_clkrst_ir_sys_root_clk_cfg;


//uart0_root_cfg, offset:0x34
typedef union
{
    u32 v;
    struct
    {
        u32  reg_uart0_root_clk_cfg_set              :1; /*[0], W1S, 1'h0, To enable new reg_uart0_root_clk_num/denom, reg_uart0_root_clk_cfg_set needs to be set when or after updating reg_uart0_root_clk_num/denom.*/
        u32  reg_uart0_root_clk_denom                :11; /*[11:1], RW, 11'h0, */
        u32  reg_uart0_root_clk_num                  :11; /*[22:12], RW, 11'h0, */
        u32  reg_uart0_root_clk_en                   :1; /*[23], RW, 1'h0, */
        u32  reg_uart0_root_clk_sel                  :2; /*[25:24], RW, 2'h0, */
        u32  reg_uart0_root_clk_sel_en               :1; /*[26], RW, 1'h0, */
        u32  reserved0                               :5; /*[31:27], RO, 5'h0, */
    }b;
}t_clkrst_uart0_root_cfg;


//lf_clk_cfg, offset:0x38
typedef union
{
    u32 v;
    struct
    {
        u32  reg_lf_clk_sel                          :2; /*[1:0], RW, 2'h0, */
        u32  reg_lf_clk_sel_en                       :1; /*[2], RW, 1'h0, */
        u32  reserved0                               :29; /*[31:3], RO, 29'h0, */
    }b;
}t_clkrst_lf_clk_cfg;


//bt_clk_cfg, offset:0x3c
typedef union
{
    u32 v;
    struct
    {
        u32  reg_bt_hclk_en                          :1; /*[0], RW, 1'h0, */
        u32  reg_dbm_hclk_en                         :1; /*[1], RW, 1'h0, */
        u32  reg_bt_ref_clk_en                       :1; /*[2], RW, 1'h0, */
        u32  reg_bt_master_clk_div_en                :1; /*[3], RW, 1'h0, */
        u32  reg_bt_master_clk_cfg_set               :1; /*[4], W1S, 1'h0, To enable new reg_bt_master_clk_div, reg_bt_master_clk_cfg_set needs to be set when or after updating reg_bt_master_clk_div.*/
        u32  reg_bt_master_clk_div                   :3; /*[7:5], RW, 3'h0, */
        u32  reserved0                               :24; /*[31:8], RO, 24'h0, */
    }b;
}t_clkrst_bt_clk_cfg;


//resetn_src0, offset:0x40
typedef union
{
    u32 v;
    struct
    {
        u32  reg_spi_presetn                         :1; /*[0], RW, 1'h1, */
        u32  reg_ir_sys_resetn                       :1; /*[1], RW, 1'h1, */
        u32  reg_ir_rstb                             :1; /*[2], RW, 1'h1, */
        u32  reg_uart0_rstb                          :1; /*[3], RW, 1'h1, */
        u32  reg_apb1_presetn                        :1; /*[4], RW, 1'h1, */
        u32  reg_dw_i2c_ic_rst_n                     :1; /*[5], RW, 1'h1, */
        u32  reg_dw_i2c_presetn                      :1; /*[6], RW, 1'h1, */
        u32  reg_aon_sleep_presetn                   :1; /*[7], RW, 1'h1, */
        u32  reg_calendar_presetn                    :1; /*[8], RW, 1'h1, */
        u32  reg_qdec_presetn                        :1; /*[9], RW, 1'h1, */
        u32  reg_pwm_resetn                          :1; /*[10], RW, 1'h1, */
        u32  reg_pwm_presetn                         :1; /*[11], RW, 1'h1, */
        u32  reg_hresetn_page_spy                    :1; /*[12], RW, 1'h1, */
        u32  reg_presetn_page_spy                    :1; /*[13], RW, 1'h1, */
        u32  reg_keypad_presetn                      :1; /*[14], RW, 1'h1, */
        u32  reg_syswdt_rstb                         :1; /*[15], RW, 1'h1, */
        u32  reg_timer_presetn                       :1; /*[16], RW, 1'h1, */
        u32  reg_cm0p_presetn                        :1; /*[17], RW, 1'h1, */
        u32  reg_presetn_aon                         :1; /*[18], RW, 1'h1, */
        u32  reg_clkrst_cfg_presetn                  :1; /*[19], RW, 1'h1, */
        u32  reg_iomux_top_presetn                   :1; /*[20], RW, 1'h1, */
        u32  reg_dbg_hst_hw_rstb                     :1; /*[21], RW, 1'h1, */
        u32  reg_dbg_hst_reg_rstb                    :1; /*[22], RW, 1'h1, */
        u32  reg_dbg_hst_uart_rstb                   :1; /*[23], RW, 1'h1, */
        u32  reg_dbg_hst_presetn                     :1; /*[24], RW, 1'h1, */
        u32  reg_apb0_hresetn                        :1; /*[25], RW, 1'h1, */
        u32  reg_hresetn_ahb_cache                   :1; /*[26], RW, 1'h1, */
        u32  reg_hresetn_spiflash                    :1; /*[27], RW, 1'h1, */
        u32  reg_hresetn_ahb_per                     :1; /*[28], RW, 1'h1, */
        u32  reg_cm0p_gpio_hresetn                   :1; /*[29], RW, 1'h1, */
        u32  reserved0                               :2; /*[31:30], RO, 2'h0, */
    }b;
}t_clkrst_resetn_src0;


//resetn_src1, offset:0x44
typedef union
{
    u32 v;
    struct
    {
        u32  reserved0                               :12; /*[11:0], RO, 12'h0, */
        u32  reg_bt_master_rstn                      :1; /*[12], RW, 1'h1, */
        u32  reg_bt_hresetn                          :1; /*[13], RW, 1'h1, */
        u32  reg_bt_ref_rstn                         :1; /*[14], RW, 1'h1, */
        u32  reg_resetn_rf                           :1; /*[15], RW, 1'h1, */
        u32  reg_uart0_presetn                       :1; /*[16], RW, 1'h1, */
        u32  reg_gpt_presetn                         :1; /*[17], RW, 1'h1, */
        u32  reg_cpu_sleep_rstb                      :1; /*[18], RW, 1'h1, */
        u32  reg_spiflash_rstn                       :1; /*[19], RW, 1'h1, */
        u32  reg_pmuif_presetn                       :1; /*[20], RW, 1'h1, */
        u32  reg_ir_presetn                          :1; /*[21], RW, 1'h1, */
        u32  reg_sys_ctrl_presetn                    :1; /*[22], RW, 1'h1, */
        u32  reg_bt_core_presetn                     :1; /*[23], RW, 1'h1, */
        u32  reg_dma_presetn                         :1; /*[24], RW, 1'h1, */
        u32  reg_ssp0_resetn                         :1; /*[25], RW, 1'h1, */
        u32  reg_dma_hresetn                         :1; /*[26], RW, 1'h1, */
        u32  reg_sysifc_presetn                      :1; /*[27], RW, 1'h1, */
        u32  reg_sysifc_hresetn                      :1; /*[28], RW, 1'h1, */
        u32  reg_mdu_presetn                         :1; /*[29], RW, 1'h1, */
        u32  reg_mdu_rstb                            :1; /*[30], RW, 1'h1, */
        u32  reg_gpt_rstb                            :1; /*[31], RW, 1'h1, */
    }b;
}t_clkrst_resetn_src1;


//cpu_stclk_cfg, offset:0x48
typedef union
{
    u32 v;
    struct
    {
        u32  reg_cpu_stclk_clk_sel                   :2; /*[1:0], RW, 2'h0, */
        u32  reg_cpu_stclk_clk_sel_en                :1; /*[2], RW, 1'h0, */
        u32  reserved0                               :29; /*[31:3], RO, 29'h0, */
    }b;
}t_clkrst_cpu_stclk_cfg;


//timer_clk_cfg, offset:0x4c
typedef union
{
    u32 v;
    struct
    {
        u32  reg_hwtimer_clk_en                      :1; /*[0], RW, 1'h1, */
        u32  reg_timer_pclk_en                       :1; /*[1], RW, 1'h1, */
        u32  reg_hwtimer_clk32k_sel                  :2; /*[3:2], RW, 2'h0, */
        u32  reg_hwtimer_clk32k_sel_en               :1; /*[4], RW, 1'h0, */
        u32  reg_syswdt_clk32k_sel                   :2; /*[6:5], RW, 2'h0, */
        u32  reg_syswdt_clk32k_sel_en                :1; /*[7], RW, 1'h0, */
        u32  reg_keypad_clk32k_sel                   :2; /*[9:8], RW, 2'h0, */
        u32  reg_keypad_clk32k_sel_en                :1; /*[10], RW, 1'h0, */
        u32  reserved0                               :21; /*[31:11], RO, 21'h0, */
    }b;
}t_clkrst_timer_clk_cfg;


//gpt_clk_cfg, offset:0x50
typedef union
{
    u32 v;
    struct
    {
        u32  reg_gpt_clk_t0_sel                      :2; /*[1:0], RW, 2'h0, */
        u32  reg_gpt_clk_t0_sel_en                   :1; /*[2], RW, 1'h0, */
        u32  reserved0                               :29; /*[31:3], RO, 29'h0, */
    }b;
}t_clkrst_gpt_clk_cfg;


//dbg_hst_clk_cfg, offset:0x54
typedef union
{
    u32 v;
    struct
    {
        u32  reg_dbg_hst_uart_clk_denom              :11; /*[10:0], RW, 11'h0, */
        u32  reg_dbg_hst_uart_clk_num                :11; /*[21:11], RW, 11'h0, */
        u32  reg_dbg_hst_en                          :1; /*[22], RW, 1'h0, */
        u32  reg_dbg_hst_uart_clk_ld_cfg_set         :1; /*[23], W1S, 1'h0, To enable new reg_dbg_hst_uart_clk_num/denom, reg_dbg_hst_uart_clk_cfg_set needs to be set when or after updating reg_dbg_hst_uart_clk_num/denom.*/
        u32  reserved0                               :8; /*[31:24], RO, 8'h0, */
    }b;
}t_clkrst_dbg_hst_clk_cfg;


//cpu_root_32k_cfg, offset:0x58
typedef union
{
    u32 v;
    struct
    {
        u32  reg_cpu_root_clk_32k_sel                :2; /*[1:0], RW, 2'h0, */
        u32  reg_cpu_root_clk_32k_sel_en             :1; /*[2], RW, 1'h0, */
        u32  reserved0                               :29; /*[31:3], RO, 29'h0, */
    }b;
}t_clkrst_cpu_root_32k_cfg;

typedef struct
{
    volatile    t_clkrst_cpu_sys_clk_cfg                cpu_sys_clk_cfg;
    volatile    t_clkrst_apb0_clk_force_cfg             apb0_clk_force_cfg;
    volatile    t_clkrst_apb1_clk_force_cfg             apb1_clk_force_cfg;
    volatile    t_clkrst_ahb_perl_clk_enable_cfg0       ahb_perl_clk_enable_cfg0;
    volatile    t_clkrst_apb0_clk_enable_cfg            apb0_clk_enable_cfg;
    volatile    t_clkrst_apb1_clk_enable_cfg            apb1_clk_enable_cfg;
    volatile    t_clkrst_mem_clk_cfg                    mem_clk_cfg;
    volatile    t_clkrst_hf0_hf1_cfg                    hf0_hf1_cfg;
    volatile    t_clkrst_root_clk_cfg                   root_clk_cfg;
    volatile    t_clkrst_cpu_root_cfg                   cpu_root_cfg;
    volatile    t_clkrst_spiflash_root_cfg              spiflash_root_cfg;
    volatile    t_clkrst_i2c_root_clk_cfg               i2c_root_clk_cfg;
    volatile    t_clkrst_ir_sys_root_clk_cfg            ir_sys_root_clk_cfg;
    volatile    t_clkrst_uart0_root_cfg                 uart0_root_cfg;
    volatile    t_clkrst_lf_clk_cfg                     lf_clk_cfg;
    volatile    t_clkrst_bt_clk_cfg                     bt_clk_cfg;
    volatile    t_clkrst_resetn_src0                    resetn_src0;
    volatile    t_clkrst_resetn_src1                    resetn_src1;
    volatile    t_clkrst_cpu_stclk_cfg                  cpu_stclk_cfg;
    volatile    t_clkrst_timer_clk_cfg                  timer_clk_cfg;
    volatile    t_clkrst_gpt_clk_cfg                    gpt_clk_cfg;
    volatile    t_clkrst_dbg_hst_clk_cfg                dbg_hst_clk_cfg;
    volatile    t_clkrst_cpu_root_32k_cfg               cpu_root_32k_cfg;
}t_hwp_clkrst;

#define hwp_clk_rst 		    ((t_hwp_clkrst*)0x4010c000)

#endif
